View MAX5115_2757010.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX5115/max5116 quad, 8-bit, digital-to-analog converters (dacs) feature nonvolatile registers. these nonvolatile registers store the dac operating modes and output states, allowing the dacs to initialize to specified configurations at power-up. precision on-chip output buffers swing rail-to-rail, and provide 8? settling time. the i 2 c*-compatible, 2-wire serial interface allows for a maximum clock frequency of 400khz. the MAX5115 has independent high and low reference inputs allowing maximum output voltage range flexibili- ty. the max5116 has single high and low reference inputs for all dacs to minimize trace count and save board space. the reference rails accept voltage inputs that range from ground to the positive supply rail. the devices operate from a single +2.7v to +5.25v sup- ply and consume 200? per dac. a software-controlled power-down mode decreases supply current to less than 25?. a software-controlled mute mode sets each dac, or both dacs simultaneously, to their respective refl_ voltages. the max5116 also includes an asyn- chronous mute input, that drives all dac outputs simul- taneously to their respective refl_ voltages. the MAX5115 is available in a 20-pin qsop, and the max5116 is available in a 16-pin qsop package. both devices are specified for operation over the extended (-40? to +85?) temperature range. applications digital gain and offset adjustments programmable attenuators portable instruments power-amp bias control ate calibration laser biasing features ? nonvolatile registers initialize dacs to stored states ? +2.7v to +5.25v single-supply operation ? quad 8-bit dacs with independent high and low reference inputs ? rail-to-rail output buffers ? low 200a per dac supply current ? power-down mode reduces supply current to 25a (max) ? 400khz, i 2 c-compatible, 2-wire serial interface ? asynchronous mute input (max5116) ? small 16-/20-pin qsop packages MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface ________________________________________________________________ maxim integrated products 1 ordering information 19-3586; rev 0; 2/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package reference inputs MAX5115 eep -40? to +85? 20 qsop 4 max5116 eee -40? to +85? 16 qsop 1 *purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associate companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification defined by philips. pin configuration and typical operating circuit appear at end of data sheet. dac0 nonvolatile/ volatile registers dac1 nonvolatile/ volatile registers out0 out1 scl gnd refl v dd refh sda a3 a2 a1 2-wire serial interface/ control mute max5116 a0 dac2 nonvolatile/ volatile registers dac3 nonvolatile/ volatile registers out2 out3 dac0 dac1 dac2 dac3 simplified diagram
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.) v dd , a0, a1, a2, a3, scl, sda, mute .................-0.3v to +6.0v out0, out1, out2, out3, refh0, refh1, refh2, refh3, refh, refl0, refl1, refl2, refl3, refl .......................................................-0.3v to (v dd + 0.3v) maximum current into any pin .........................................?0ma power dissipation (t a = +70?) 16-pin qsop (derate 8.3mw/? above +70?)...........667mw 20-pin qsop (derate 9.1mw/? above +70?)...........727mw operating temperature range ...........................-40? to +85? junction temperature .....................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v dd = +2.7v to +5.25v, gnd = 0, refh_ = v dd , refl_ = gnd, r load = 5k ? , c l = 100pf, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = +3.0v and t a = +25?.) (note 1) parameter symbol conditions min typ max units static accuracy resolution 8 bits code range 0a hex to f0 hex ? integral nonlinearity inl full code range ? lsb code range 0a hex to f0 hex ?.5 differential nonlinearity (note 2) dnl full code range ? lsb offset error zce code = 0a hex ?0 mv offset temperature coefficient code = 0a hex ?0 ?/? gain error code = f0 hex (note 3) ? lsb gain-error temperature coefficient code = f0 hex ?.002 lsb/? power-supply rejection ratio psrr code = ff hex or 0a hex, v refh_ = 2.5v, v refl_ = 0, f = dc 1 lsb/v reference input (refh_, refl_, refh, refl) input voltage range v refh_ , v refl_ v refh_ v refl_ 0v dd v MAX5115 320 460 600 input resistance max5116 80 115 150 k ? input-resistance temperature coefficient ?5 ppm/? input capacitance 10 pf dac outputs (out_) load regulation code = f0 hex, r load 5k ? ?.5 1 lsb output leakage dac powered down, not muted ?0 ? amplifier output resistance 0.5v v out_ (v dd - 0.5v) 0.5 ? digital inputs (a_, mute ) 2.7v v dd < 3.6v 0.7 x v dd input high voltage (note 4) v ih 3.6v v dd 5.25v 2.52 v
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +5.25v, gnd = 0, refh_ = v dd , refl_ = gnd, r load = 5k ? , c l = 100pf, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = +3.0v and t a = +25?.) (note 1) parameter symbol conditions min typ max units 2.7v v dd < 3.6v 0.3 x v dd input low voltage (note 4) v il 3.6v v dd 5.25v 1.1 v input hysteresis v hys 0.05 x v dd v input leakage current i in v in = 0 or v dd ? ? input capacitance c in 10 pf digital output (sda) i sink = 3ma 0.4 output low voltage v ol i sink = 6ma 0.6 v tri-state leakage i l ? ? tri-state output capacitance c out 15 pf dynamic performance scl to out_ settling t cos (note 5) 8 s crosstalk (note 6) 55 db v refh_ = 2.5v p-p at 1khz 65 multiplying signal-to-noise plus distortion sinad v refh_ = 2.5v p-p at 10khz 52 db multiplying bandwidth v refh_ = 0.5v p-p , 3db bandwidth 325 khz reference feedthrough v refh_ = 2.5v p-p at 10khz (note 7) 88 db clock feedthrough 2.5 nvs output noise e n 800 nv/ hz power-up time t sdr from power-down state 4 s power-down time t sdn 1.5 ? interface ports (scl, sda) v il 0.3 x v dd input voltage v ih 0.7 x v dd v input hysteresis v hys 0.05 x v dd v input current i in ? ? input capacitance c in 5pf power supplies power-supply voltage v dd 2.70 5.25 v normal operation 0.8 1.3 supply current i dd i load = 0, digital inputs at gnd or v dd during nonvolatile write 2 ma power-down current 25 ?
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +2.7v to +5.25v, gnd = 0, refh_ = v dd , refl_ = gnd, r load = 5k ? , c l = 100pf, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = +3.0v and t a = +25?.) (note 1) parameter symbol conditions min typ max units digital timing (figure 4, note 8) scl clock frequency f scl 400 khz setup time for start condition t su:sta 0.6 ? hold time for start condition t hd:sta 0.6 ? scl high time t high 0.6 ? scl low time t low 1.3 ? data setup time t su:dat 100 ns data hold time t hd:dat 0 0.9 ? sda, scl rise time t r 300 ns sda, scl fall time t f 300 ns setup time for stop condition t su:sto 0.6 ? bus free time between a stop and start condition t buf 1.3 ? pulse width of spike suppressed t sp 50 ns maximum capacitive load for each bus line c b (note 9) 400 pf write nv register busy time (note 10) 15 ms nonvolatile memory reliability data retention t a = +85? 50 years t a = +25? 200,000 endurance t a = +85? 50,000 stores note 1: all devices are 100% production tested at t a = +25?. all temperature limits are guaranteed by design. note 2: guaranteed monotonic. note 3: gain error is defined as: where v f0,meas is the dac voltage with input code f0 hex and v f0,ideal is the ideal dac voltage with input code f0 hex or (v refh - v refl ) x (240 / 256) + v refl . note 4: the device draws higher supply current when the digital inputs are driven with voltages between (v dd - 0.5v) and (gnd + 0.5v). see supply current vs. digital input voltage in the typical operating characteristics . note 5: output settling time is measured from the 50% point of the rising edge of the last scl of the data byte to 0.5 lsb of out_? final value for a code transition from 10 hex to f0 hex. note 6: crosstalk is defined as the coupling from a dac switching from code 00 hex to code ff hex to any other dac that is in a steady state at code 00 hex. note 7: reference feedthrough is defined as the coupling from one driven reference with input code = ff hex to any other dac output with the reference of the dac at a constant value and input code = 00 hex. note 8: scl clock period includes rise and fall times t r and t f . all digital input signals are specified with t r = t f = 2ns and timed from a voltage level of (v il + v ih ) / 2. note 9: an appropriate bus pullup resistance must be selected depending on board capacitance. refer to the document linked to this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf. note 10: the busy time begins from the initiation of the stop pulse. 256 00 ?? () ,, _ v zce v v f meas f ideal refh
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface _______________________________________________________________________________________ 5 integral nonlinearity vs. input code MAX5115/5116 toc01 input code integral nonlinearity (lsb) 192 128 64 -0.5 0 0.5 1.0 1.5 2.0 -1.0 0256 integral nonlinearity vs. supply voltage MAX5115/5116 toc02 supply voltage (v) integral nonlinearity (lsb) 5.0 4.5 3.0 3.5 4.0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0 2.5 5.5 integral nonlinearity vs. temperature MAX5115/5116 toc03 temperature ( c) integral nonlinearity (lsb) 60 35 -15 10 0.25 0.50 0.75 1.00 1.50 1.25 1.75 2.00 0 -40 85 differential nonlinearity vs. input code MAX5115/5116 toc04 input code differential nonlinearity (lsb) 192 128 64 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 0256 differential nonlinearity vs. supply voltage MAX5115/5116 toc05 supply voltage (v) differential nonlinearity (lsb) 5.0 4.5 4.0 3.5 3.0 -1.25 -1.00 -0.75 -0.50 -0.25 0 -1.50 2.5 5.5 differential nonlinearity vs. temperature MAX5115/5116 toc06 temperature ( c) differential nonlinearity (lsb) 60 35 10 -15 -1.1 -1.0 -0.9 -0.8 -1.2 -40 85 offset error vs. supply voltage MAX5115/5116 toc07 supply voltage (v) offset error (lsb) 5.0 4.5 4.0 3.5 3.0 0.2 0.3 0.4 0.5 0.1 2.5 5.5 offset error vs. temperature MAX5115/5116 toc08 temperature ( c) offset error (lsb) 60 35 10 -15 0.25 0.30 0.35 0.40 0.20 -40 85 gain error vs. supply voltage MAX5115/5116 toc09 supply voltage (v) gain error (lsb) 5.0 4.5 4.0 3.5 3.0 -0.18 -0.16 -0.14 -0.12 -0.10 -0.08 -0.06 -0.20 2.5 5.5 typical operating characteristics (v dd = +3v, v refh_ = +3v, v refl_ = gnd, r l = 5k ? , c l = 100pf, t a = +25?, unless otherwise noted.)
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 6 _______________________________________________________________________________________ gain error vs. temperature MAX5115/5116 toc10 temperature ( c) gain error (lsb) 60 35 10 -15 -0.18 -0.16 -0.14 -0.12 -0.10 -0.08 -0.20 -40 85 offset output voltage vs. output sink current MAX5115/5116 toc11 output sink current (ma) offset output voltage (v) 8 6 4 2 0.20 0.25 0.30 0.35 0.40 0.15 010 v dd = v refh_ = 5v v refl_ = 0.2v v dd = v refh_ = 3v full-scale output voltage vs. output source current MAX5115/5116 toc12 output source current (ma) full-scale output voltage (v) 12 9 6 3 2.5 3.0 3.5 4.0 4.5 5.0 2.0 015 v dd = v refh_ = 5v v dd = v refh_ = 3v supply current vs. input code MAX5115 toc13 input code supply current ( a) 192 128 64 450 500 550 600 650 700 750 800 400 0256 no load supply current vs. digital input voltage MAX5115/5116 toc14 digital input voltage (v) supply current ( a) 1000 100 no load v dd = v refh = +5v 1234 05 supply current vs. temperature MAX5115/5116 toc15 temperature ( c) supply current ( a) 60 35 10 -15 500 550 600 650 700 450 -40 85 no load c a b d a: v dd = 5v, v refh_ = 4.096v, code = ffh b: v dd = 5v, v refh_ = 4.096v, code = 00h c: v dd = 3v, v refh_ = 2.5v, code = ffh d: v dd = 3v, v refh_ = 2.5v, code = 00h typical operating characteristics (continued) (v dd = +3v, v refh_ = +3v, v refl_ = gnd, r l = 5k ? , c l = 100pf, t a = +25?, unless otherwise noted.)
supply current vs. supply voltage MAX5115/5116 toc16 supply voltage (v) supply current ( a) 5.0 4.5 3.0 3.5 4.0 525 550 575 600 625 650 675 700 500 2.5 5.5 t a = -40 c no load code = 00h t a = +85 c t a = +25 c supply current vs. reference voltage MAX5115/5116 toc17 reference voltage (v) supply current ( a) 4 3 2 1 450 500 550 600 650 700 400 05 no load v dd = 5v code = ffh v dd = 5v code = 00h v dd = 3v code = ffh v dd = 3v code = 00h reference feedthrough vs. frequency (MAX5115) MAX5115/5116 toc18 frequency (khz) reference feedthrough (db) 10,000 1000 100 10 1 0.1 -90 -80 -70 -60 -50 -40 -100 0.01 100,000 v dd = 5v v dd = 3v measured at out1, v refl1 = v refl0 = gnd, v refh1 = v dd, v refh0 = 2.5v p-p , signal centered at v dd /2, out0 = ffh, out1 = 00h, no load MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface _______________________________________________________________________________________ 7 startup glitch MAX5115/5116 toc19 nv register previously set to code ffh gnd gnd out_ 1v/div v dd 2v/div 100 s/div power-down transition MAX5115/5116 toc20 gnd gnd out_ 500mv/div scl 2v/div 400ns/div 26 power-up transition MAX5115/5116 toc21 gnd gnd out_ 500mv/div scl 2v/div 1 s/div 25 26 27 positive carry transition MAX5115/5116 toc22 out_ 50mv/div ac-coupled 4 s/div negative carry transition MAX5115/5116 toc23 out_ 50mv/div ac-coupled 2 s/div positive settling time MAX5115/5116 toc24 out_ 1v/div 2 s/div scl 2v/div gnd gnd 25 26 27 typical operating characteristics (continued) (v dd = +3v, v refh_ = +3v, v refl_ = gnd, r l = 5k ? , c l = 100pf, t a = +25?, unless otherwise noted.)
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 8 _______________________________________________________________________________________ pin description pin MAX5115 max5116 name function 1 2 a2 address select 2. connect to v dd or gnd to set the device address. 2 3 a1 address select 1. connect to v dd or gnd to set the device address. 3 4 a0 address select 0. connect to v dd or gnd to set the device address. 4 refh1 dac1 high reference input. refh1 must be equal to or greater than refl1. 5 refl1 dac1 low reference input. refl1 must be equal to or less than refh1. 6 6 out1 dac1 output. out1 is buffered with a unity-gain amplifier. 7 refh2 dac2 high reference input. refh2 must be equal to or greater than refl2. 8 refl2 dac2 low reference input. refl2 must be equal to or less than refh2. 9 7 out2 dac2 output. out2 is buffered with a unity-gain amplifier. 10 8 gnd ground 11 10 out3 dac3 output. out3 is buffered with a unity-gain amplifier. 12 refl3 dac3 low reference input. refl3 must be equal to or less than refh3. 13 refh3 dac3 high reference input. refh3 must be equal to or greater than refl3. 14 11 out0 dac0 output. out0 is buffered with a unity-gain amplifier. 15 refl0 dac0 low reference input. refl0 must be equal to or less than refh0. 16 refh0 dac0 high reference input. refh0 must be equal to or greater than refl0. 17 14 scl serial-clock input. connect scl to v dd through a 2.4k ? pullup resistor. 18 15 v dd positive-power input. connect v dd to a +2.7 to +5.25v power supply. bypass v dd to gnd with a 0.1? capacitor as close to the device as possible. 19 16 sda serial data input/output. connect sda to v dd through a 2.4k ? pullup resistor. 20 1 a3 address select 3. connect to v dd or gnd to set the device address. 5 n.c. no connection. not internally connected. ? mute active-low mute input. connect mute low to drive all dac outputs to their respective reference low voltages. connect mute to v dd for normal operation. 12 refl dac low reference input. refl must be equal to or less than refh. 13 refh dac high reference input. refh must be equal to or greater than refl. typical operating characteristics (continued) (v dd = +3v, v refh_ = +3v, v refl_ = gnd, r l = 5k ? , c l = 100pf, t a = +25?, unless otherwise noted.) output crosstalk MAX5115/5116 toc27 out1 10mv/div ac-coupled 2 s/div scl 2v/div gnd gnd out0 2v/div out1 set to 7fh clock feedthrough MAX5115/5116 toc26 out_ 10mv/div ac-coupled 1 s/div scl 2v/div gnd out_ set to 7fh negative settling time MAX5115/5116 toc25 out_ 1v/div 2 s/div scl 2v/div gnd gnd 25 26 27
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface _______________________________________________________________________________________ 9 dac0 nonvolatile register dac1 nonvolatile register refl0 out0 17 18 10 19 16 15 14 4 5 6 20 1 2 out1 scl gnd v dd sda a3 a2 a1 2-wire serial interface/ control refh0 refl1 refh1 dac0 volatile register dac1 volatile register MAX5115 dac0 dac1 3 a0 dac2 nonvolatile register dac3 nonvolatile register refl2 out2 7 8 9 13 12 11 out3 refh2 refl3 refh3 dac2 volatile register dac3 volatile register dac2 dac3 por figure 1. MAX5115 functional diagram
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 10 ______________________________________________________________________________________ dac0 nonvolatile register dac1 nonvolatile register out0 14 15 13 812 16 11 6 1 2 3 out1 scl gnd refl v dd refh sda a3 a2 a1 2-wire serial interface/ control dac0 volatile register dac1 volatile register max5116 dac0 dac1 4 a0 9 mute dac2 nonvolatile register dac3 nonvolatile register out2 7 10 out3 dac2 volatile register dac3 volatile register dac2 dac3 por figure 2. max5116 functional diagram
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface ______________________________________________________________________________________ 11 detailed description the MAX5115/max5116 8-bit dacs feature internal, nonvolatile registers that store the dac states for initial- ization during power-up. these devices consist of resis- tor-string dacs, rail-to-rail output buffers, a shift register, power-on reset (por) circuitry, and volatile and nonvolatile memory registers (figures 1 and 2). the shift register decodes the control and address bits, routing the data to the proper registers. writing data to a selected volatile register immediately updates the dac outputs. the volatile registers retain data as long as the device is powered. removing power clears the volatile regis- ters. the nonvolatile registers retain data even after power is removed. on startup, when power is first applied, data from the nonvolatile registers is trans- ferred to the volatile registers to automatically initialize the device. read data from the nonvolatile or volatile registers using the 2-wire serial interface. dac operation the MAX5115/max5116 use a dac matrix decoding architecture that saves power. a resistor string divides the difference between the external reference voltages, v refh_ and v refl_ . row and column decoders select the appropriate tap from the resistor string, providing the equivalent analog voltage. the resistor string pre- sents a code-independent input impedance to the ref- erence and guarantees a monotonic output. figure 3 shows a simplified diagram of one dac. output buffer amplifiers the MAX5115/max5116 analog outputs are internally buffered by a precision unity-gain amplifier. the outputs swing from gnd to v dd with a v refl_ -to-v refh_ output transition. the amplifier outputs typically settle to ?.5 lsb in 8? when loaded with 5k ? in parallel with 100pf. dac registers the MAX5115/max5116 feature two registers per dac, a volatile and a nonvolatile register, that store the dac data. the volatile dac register holds the current value of each dac. write data to the volatile registers directly from the 2-wire serial interface or by loading the previ- ously stored data from the respective nonvolatile regis- ter. clear the volatile registers by removing power to the device. the volatile registers are read/write. the nonvolatile register retains the dac values even after power is removed. read stored data using the 2- wire serial interface. on power-up, the devices auto- matically initialize with data stored in the nonvolatile registers. the nonvolatile registers are read/write and programmed to all zeros at the factory. refh_ refl_ r1 r15 r16 r255 r0 d7 d6 d5 d4 dac msb decoder d3 d0 d2 d1 lsb decoder figure 3. dac simplified circuit diagram
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 12 ______________________________________________________________________________________ serial interface the MAX5115/max5116 feature an i 2 c-compatible, 2- wire serial interface consisting of a bidirectional serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communication between the MAX5115/max5116 and the master at rates up to 400khz (figure 4). the master (typically a microcon- troller) initiates data transfer on the bus and generates scl. sda and scl require pullup resistors (2.4k ? or greater; see the typical operating circuit ). optional resistors (24 ? ) in series with sda and scl protect the device inputs from high-voltage spikes on the bus lines. series resistors also minimize crosstalk and undershoot of the bus signals. i 2 c compatibility the MAX5115/max5116 are compatible with existing i 2 c systems. scl and sda are high-impedance inputs; sda has an open-drain output. the typical operating circuit shows an i 2 c application. the communication protocol supports standard i 2 c 8-bit communications. the general call address is ignored, and cbus formats are not supported. the devices?addresses are com- patible with 7-bit i 2 c addressing protocol only. no 10- bit address formats are supported. bit transfer one data bit transfers during each scl rising edge. nine clock cycles are required to transfer the data into or out of the MAX5115/max5116. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high are read as control signals (see the start and stop conditions section). both sda and scl idle high. start and stop conditions the master initiates a transmission with a start condi- tion (s), a high-to-low transition on sda with scl high. the master terminates a transmission with a stop condi- tion (p), a low-to-high transition on sda while scl is high (figure 5). a start condition from the master signals the beginning of a transmission to the MAX5115/ max5116. the master terminates transmission by issu- ing a stop condition. the stop condition frees the bus. if a repeated start condition (sr) is generated instead of a stop condition, the bus remains active. early stop conditions the MAX5115/max5116 recognize a stop condition at any point during transmission except if a stop condi- tion occurs in the same high pulse as a start condi- tion (figure 6). this condition is not a legal i 2 c format. repeated start conditions a repeated start (sr) condition is used when the bus master is writing to several i 2 c devices and does not want to relinquish control of the bus. the MAX5115/max5116 serial interface supports continu- ous write operations with an sr condition separating them. continuous read operations require sr conditions because of the change in direction of data flow. t hd:sta t high t r t f t hd:sta s sr ack scl sda t su:sta t su:sto t r t f t buf t low t su:dat t hd:dat ps parameters are measured from 30% to 70%. figure 4. 2-wire serial-interface timing diagram sp sr scl sda figure 5. start and stop conditions
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface ______________________________________________________________________________________ 13 acknowledge bit (ack) and not- acknowledge bit (nack) successful data transfers are acknowledged with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the MAX5115/max5116 (slave) generate acknowledge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 7). to generate a not acknowledge, the receiver allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer, the master should reattempt com- munication at a later time. slave address a master initiates communication with a slave device by issuing a start condition followed by a slave address (figure 8). the slave address consists of 7 address bits and a read/write bit (r/ w ). when idle, the device continuously waits for a start condition fol- lowed by its slave address. when the device recog- nizes its slave address, it acquires the data byte and executes the command. the first 3 bits (msbs) of the slave address have been factory programmed and are always 010. connect a3?0 to v dd or gnd to program the remaining 4 bits of the slave address. the least sig- nificant bit (lsb) of the address byte (r/ w ) determines whether the master is writing to or reading from the MAX5115/max5116. (r/ w = 0 selects a write condition. r/ w = 1 selects a read condition.) after receiving the address, the MAX5115/max5116 (slave) issues an acknowledge by pulling sda low for one clock cycle. scl sda stop start scl sda illegal stop start illegal early stop condition legal stop condition figure 6. early stop conditions 189 acknowledge not acknowledge scl s sda figure 7. acknowledge and not-acknowledge bits scl sda 123 0 a3 1 0 89 4567 a2 a1 a0 r/w ack acknowledge s figure 8. slave address byte
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 14 ______________________________________________________________________________________ write cycle the write command requires 27 clock cycles. in write mode (r/ w = 0), the command byte that follows the address byte controls the MAX5115/max5116 (table 1). for a write function, set bits c7 and c6 to zero. set bits c5 and c4 to select the volatile or nonvolatile register (table 2). set bits c3?0 to select the respective dac register (table 3). the registers update on the rising edge of the 26th scl pulse. prematurely aborting the write cycle does not update the dac. see table 4 for a summary of the write commands. read cycle a read command requires 36 clock cycles. in read mode, the MAX5115/max5116 send the contents of the volatile and nonvolatile registers to the bus. reading a register requires a repeated start (sr) condition. to read a register first, write a read command (r/ w = 0, figure 9). set the most significant 2 bits of the com- mand byte to 10 (c7 = 1 and c6 = 0). set bits c5 and c4 to read from either the volatile or nonvolatile register (table 5). set bits c3?0 to select the desired dac register (table 6). after the command byte, send a (sr) condition followed by the address of the device (r/ w = 1). the MAX5115/max5116 then acknowledge and send the data on the bus. mute/power-down mode the MAX5115/max5116 feature software-controlled mute and power-down modes for each dac. the power-down mode places the dac output in a high- impedance state and reduces quiescent-current con- sumption (25? (max) with all dacs powered-down). s0 1 0 a3 a2 a1 a0 a3 a2 a1 a0 10nvvr3r2r1r0 c7 c6 c5 c4 c3 c2 c1 c0 sr 0 1 0 msb lsb msb lsb lsb msb ack ack ack nack r/w = 1 d7 d6 d5 d4 d3 d2 d1 d0 p msb lsb address and command bytes generated by master device data byte generated by MAX5115/max5116 nack generated by master device r/w = 0 figure 9. example read word data sequence address byte command byte data byte start r/ w c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 stop master sda s010 a 3 a 2 a 1 a 0 0 c 7 c 6 n v v r 3 r 2 r 1 r 0 d7?0 p slave sda a c k a c k a c k table 1. write operation
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface ______________________________________________________________________________________ 15 mute drives the selected dac output to the correspond- ing refl_ voltage. the volatile dac registers retain data and the output returns to its previous state when mute is disabled. the max5116 also features an asynchronous mute input that mutes all dacs simultaneously. the volatile and nonvolatile registers remain active while the MAX5115/max5116 are in mute and power- down modes. writing to or reading from the volatile or nonvolatile registers does not remove the MAX5115/ max5116 from mute or power-down mode. writing or transferring data to the volatile registers while the device is muted or powered down updates the dac outputs to the new state upon exiting mute or power- down mode. mute/power-down register and operation separate nonvolatile and volatile control registers store and update the state of the mute/power-down mode for each dac. tables 7 and 8 show how to access and control each register. register access is gained by set- ting control bits c3?0 to 0100. bits c5 and c4 indi- cate whether the nonvolatile or volatile control register is accessed. the volatile register maintains data while nonvolatile (nv) volatile (v) function 00 transfer data from nvreg_ to vreg_ 0 1 write to vreg_ 1 0 write to nvreg_ 1 1 write to nvreg and vreg_ table 2. volatile and nonvolatile write selection r3 r2 r1 r0 function 0 0 0 0 dac0 0 0 0 1 dac1 0 0 1 0 dac2 0 0 1 1 dac3 1 1 1 1 all dacs* table 3. dac write selection *this option is only valid for a write to all volatile registers. data byte address byte command byte msb lsb command s t a r t r/ w a c k c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k stop write vreg_ s 0 0 0 0 1 r 3 r 2 r 1 r 0 d7?0 p write all vreg_* s 0 00011111 d7?0 p write nvreg_ s 0 0010 r 3 r 2 r 1 r 0 d7?0 p write vreg_ and nvreg_ s 0 0011 r 3 r 2 r 1 r 0 d7?0 p transfer nvreg_ to vreg_ s 0 0000 r 3 r 2 r 1 r 0 ? table 4. write-command summary *this option is only valid for a write to all volatile registers.
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 16 ______________________________________________________________________________________ the device remains powered. the nonvolatile register maintains data even after power is removed. the MAX5115/max5116 start up (power first applied) by transferring the mute/power-down from the nonvolatile to the volatile control register. the nonvolatile control register is set to 00 hex at the factory. power-on reset power-on reset (por) circuitry controls the initializa- tion of the MAX5115/max5116. a power-on reset loads the volatile registers with the data stored in the nonvolatile registers. this initialization period takes 500? (typ). during this time, the dac outputs are held in mute mode. at the completion of the initialization period, the dac outputs update in accordance with the configuration register. dac data the 8-bit dac data is decoded as offset binary, msb first, with 1 lsb = (v refh_ - v refl_ ) / 256, and convert- ed into the corresponding analog voltage as shown in table 9. nonvolatile (nv) volatile (v) function 0 1 read from vreg_ 1 0 read from nvreg_ table 5. volatile and nonvolatile read selection r3 r2 r1 r0 function 0 0 0 0 dac0 0 0 0 1 dac1 0 0 1 0 dac2 0 0 1 1 dac3 table 6. dac read selection data byte address byte command byte msb lsb command s t a r t r/ w a c k c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k stop write vctl s 0 0 0 0 1 0 1 0 0 control register* p write nvctl s 0 0 0 1 0 0 1 0 0 control register* p write vctl and nvctl s 0 0 0 1 1 0 1 0 0 control register* p transfer nvctl to vctl s 0 0 0 0 0 0 1 0 0 control register* p table 7. mute/power-down operation *see mute/power-down control register (table 8). bit in register d7 (msb) d6 d5 d4 d3 d2 d1 d0 (lsb) controlling function mute dac3 mute dac2 mute dac1 mute dac0 power-down dac3 power-down dac2 power-down dac1 power-down dac0 table 8. mute/power-down control register
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface ______________________________________________________________________________________ 17 applications information dac linearity and offset voltage the output buffer can have a negative input offset volt- age that would normally drive the output negative, but with no negative supply, the output remains at gnd (figure 10). determine linearity using the end-point method, measuring between code 10 (0a hex) and code 240 (f0 hex) after calibrating the offset and gain error (figure 10). external voltage reference the MAX5115 features two reference inputs for each dac (refh_ and refl_). the max5116 uses a single reference for all four dacs (refh and refl). refh_ sets the full-scale voltage, while refl_ sets the zero code output. the MAX5115 has a 460k ? typical input impedance that is independent of the code. the max5116 has a 115k ? typical input impedance that is independent of the code. power sequencing the voltage applied to refh_ and refl_ should not exceed v dd at any time. if proper power sequencing is not possible, connect an external schottky diode between refh_, refl_, and v dd to ensure compliance with the absolute maximum ratings. do not apply signals to the digital inputs before the device is fully powered. power-supply bypassing and ground management digital or ac transient signals on gnd can create noise at the analog output. return gnd to the highest-quality ground available. bypass v dd with a 0.1? capacitor, located as close to the device as possible. bypass refh_ and refl_ to gnd with 0.1? capacitors. careful pc board ground layout minimizes crosstalk between the dac outputs and digital inputs. dac code output voltage (v) 1111 1111 1000 0000 0000 0001 0000 0000 v refl_ table 9. unipolar code output voltage o dac code negative offset output voltage figure 10. effect of negative offset (single supply) 255 256 ? + () __ _ vv v refh refl refl 128 256 ? + ( __ _ vv v refh refl refl 256 ? + () __ _ vv v refh refl refl
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface 18 ______________________________________________________________________________________ r p r p v dd v dd v dd c sda scl sda refh0 scl v dd out0 out2 r s * r s * r s * r s * refh2 refl0 a3 a0 sda refh scl refl address 0101 111 address 0101 110 *optional MAX5115 MAX5115 out3 refh3 out1 refh1 refl1 a2 refl2 a1 refl3 refh0 out0 out2 refh2 refl0 a3 a0 out3 refh3 out1 refh1 refl1 a2 refl2 a1 refl3 typical operating circuit top view 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 a3 sda v dd scl refh refl out0 out3 mute max5116 qsop a2 a1 out1 a0 n.c. out2 gnd 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 a3 sda v dd scl refh1 a0 a1 a2 refh0 refl0 out0 refh3 refl2 refh2 out1 refl1 12 11 9 10 refl3 out3 gnd out2 MAX5115 qsop pin configurations chip information transistor count: 40,209 process: bicmos
MAX5115/max5116 nonvolatile, quad, 8-bit dacs with 2-wire serial interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps e 1 1 21-0055 package outline, qsop .150", .025" lead pitch

▲Up To Search▲

Price & Availability of MAX5115

	To Download MAX5115 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .